1. Field of the Invention
The present invention relates to a semiconductor integrated circuit, more particularly to a technology for controlling unnecessary power consumption in a flip-flop circuit and further ensuring a high-speed operation when necessary.
2. Description of the Related Art
The range of a conventional D-flip-flop includes a dynamic type, static type, sense amplifier type and the like. FIG. 18 of IEEE Journal Of Solid-State Circuits, Vol. 34, No. 4, April, 1999, discloses a semi dynamic flip-flop, which represents a circuit example capable of realizing a high-speed operation therein. FIG. 13 of the present invention shows a D-flip-flop of the dynamic type as the circuit example thereof. The dynamic-type D-flip-flop consumes a large quantity of power even when an input data signal D and an output data signal NQ are in a same state, thereby resulting in a large mean current.
No. 2001-267889 of the Publication of the Unexamined Patent Applications discloses a circuit example achieving a reduced power consumption. The circuit example is a flip-flop of the static type attached by a clock signal control function. FIG. 14 shows an example of the static type D-flip-flop. In the static-type flip-flop circuit, an internal clock is halted when the input data signal D and output data signal Q are in a same state to thereby result in a reduced power consumption due to halting an internal operation. A problem in the static-type flip-flop circuit is that a setup time is large and an operation at a higher speed is difficult.
Abreast of an advancing miniaturization of semiconductor elements, a semiconductor substrate is provided with a sharow trench isolation region (Sharow Trench Isolation) in order to isolate respective transistors or circuit blocks. In forming the sharow trench isolation region, when a distortion is generated in a lattice constant of a molecular structure, which is a characteristic of a diffusion region constituting a source or drain of an MOS-type transistor, the diffusion region of the transistor formed in a neighboring area of the sharow trench isolation region is subject to a stress. The stress causes a mobility of an electric charge to be degraded, thereby resulting in a lower current capacity (Ids) and increased threshold voltage (Vth).